1. Field of the Invention
The present invention relates generally to a charging and discharging integration circuit in which a capacitor is alternately charged and discharged according to input signals transferred at signal distances to sum up the signal distances in analogue technique, and more particularly to a charging and discharging integration circuit in which the signal distances are summed up with high accuracy and the number of external terminals connecting the integration circuit with external elements is reduced in cases where the charging and discharging integration circuit is manufactured as an element of an integrated circuit.
2. Description of the Prior Art
In a conventional charging and discharging integration circuit utilized for an ignition-advance control of an engine (Publication of Japanese Patent Application No. 62-17671), a capacitor of the integration circuit is alternately charged and discharged according to input signals respectively transferred in synchronization with the number of rotations of a piston or a rotor in the engine. An example of the conventional charging and discharging integration circuit is shown in FIG. 1.
2.1. First Previously Proposed Art
As shown in FIG. 1, a conventional charging and discharging integration circuit 11 is provided with a constant voltage source 12 placed in an integrated circuit (IC) package 13, a constant charging current circuit 14 placed in the IC package 13 for flowing a constant charging current, a capacitor element 15 placed outside the IC package 13 for accumulating an electric charge supplied from the constant voltage source 12 through the constant charging current circuit 14 and discharging the electric charge, a charging switch 16 placed in the IC package 13 for connecting the circuit 14 with the capacitor element 15, a constant discharging current circuit 17 placed in the IC package 13 for flowing a constant discharging current to discharge the electric charge in the capacitor element 15, a discharging switch 18 placed in the IC package 13 for connecting the capacitor element 15 with the constant discharging current circuit 17, an external charging resistor 19 placed outside the IC package 13 for adjusting the constant charging current flowing through the constant charging circuit 14, and an external discharging resistor 20 placed outside tile IC package 13 for adjusting the constant discharging current flowing through the constant discharging current circuit 17. The external charging resistor 19 is connected with an external terminal T1 of the IC package 13 and is grounded, and the external discharging resistor 20 is connected with an external terminal T2 of the IC package 13. Because values R'c, R'd of the resistors 19, 20 are precisely adjusted, it is necessary to place the resistors 19, 20 outside the IC package 13. An external element (not shown) is connected with an external terminal T3 of the IC package 13 to receive the electric charge from the constant voltage source 12, the capacitor element 15 is grounded and is connected with an external terminal T4 of the IC package 13, and the constant discharging current circuit 17 is connected with an external terminal T5 of the IC package 13 and is grounded to discharge the electric charge.
FIG. 2 is a detail circuit view of the conventional charging and discharging integration circuit 11 shown in FIG. 1.
As shown in FIG. 2, the constant voltage source 12 is provided with a resistor 21 connected to an electric source (not shown) and a zener diode 22. A constant voltage Vcc is supplied from the constant voltage source 12. The constant charging current circuit 14 is concretized by a current mirror circuit composed of a first PNP transistor 23 and a second PNP transistor 24 of which base terminals are connected to each other. A collector terminal and the base terminal in the first PNP transistor 23 is directly connected. A collector terminal of the second PNP transistor 24 is connected with the capacitor element 15 through a charging line Lc, and the external charging resistor 19 is connected to the collector terminal of the first PNP transistor 23. Because the constant charging current flowing through the charging line Lc is substantially equal to a current flowing through the external charging resistor 19, the constant charging current is adjusted by the external charging resistor 19.
The charging switch 16 is provided with a first resistor 26, a second resistor 27 and a switching NPN transistor 28 serially connected in that order between the constant voltage source 12 and the ground, and a short PNP transistor 29 of which a base terminal is connected to a line between the first and second resistors 26, 27. In cases where the switching NPN transistor 28 is set in a conducting condition by applying a positive voltage to a base terminal of the transistor 28, the base terminal of the short PNP transistor 29 is lowered, so that the short PNP transistor 29 is set in a conducting condition. Therefore, the emitter and base terminals of the second PNP transistor 24 are short-circuited, and tile constant charging current flowing through the charging line Lc is stopped. That is, the operation of the constant charging current circuit 14 is halted. In other words, the charging switch 16 is switched off.
The constant discharging current circuit 17 is concretized by a current mirror circuit composed of a first NPN transistor 30 and a second NPN transistor 31 of which base terminals are connected to each other. Collector and base terminals of the second NPN transistor 31 are directly connected. A collector terminal of the first NPN transistor 30 is connected with the capacitor element 15 through the charging line Lc, and the external discharging resistor 20 is connected to the collector terminal of the second NPN transistor 31. Because the constant discharging current flowing from the capacitor element 15 to an emitter terminal of the first NPN transistor 30 is substantially equal to a current flowing from the external discharging resistor 20, the constant discharging current is adjusted by the external discharging resistor 20.
The discharging switch 18 is concretized by a switching NPN transistor 32 of which a collector terminal is connected to the collector terminal of the second NPN transistor 31 and an emitter terminal is connected to an emitter terminal of the transistor 31. In cases where the switching NPN transistor 32 is set in a conducting condition, the emitter and base terminals of the first NPN transistor 30 are short-circuited, and the constant discharging current flowing from the transistor 30 is stopped. That is, the operation of the constant discharging current circuit 17 is halted. In other words, the discharging switch 18 is switched off.
In the above configuration of the conventional charging and discharging integration circuit 11, the operation of the charging and discharging integration circuit 11 is described with reference to FIG. 3.
In a charging period, the switching NPN transistor 28 is set in a non-conducting condition to switch on the charging switch 16, and the switching NPN transistor 32 is set in the conducting condition to switch off the discharging switch 18. In this case, a charged voltage Vc at the capacitor element 15 is linearly increased as shown in FIG. 3. In contrast, in a discharging period, the switching NPN transistor 28 is set in the conducting condition to switch off the charging switch 16, and the switching NPN transistor 32 is set in the non-conducting condition to switch on the discharging switch 18. In this case, the charged voltage Vc at the capacitor element 15 is linearly decreased as shown in FIG. 3.
For example, in cases where the capacitor element 15 set at a base capacitor voltage VO is charged at the constant charging current having a value Ic for a charging time t1 to reach a charged capacitor voltage Vc(t1), an equation (1) is obtained. EQU Vc(t1)=VO+Ic*t1/C (1)
Here a symbol C denotes a capacitance of the capacitor element 15. Thereafter, in cases where the capacitor element 15 charged at the charged capacitor voltage Vc(t1) is discharged at the constant discharging current having a value Id for a discharging time t2 to return to the base capacitor voltage VO, an equation (2) is obtained. EQU VO=Vc(t1)-Id*t2/C (2)
Therefore, an equation (3) is obtained from the equations (1) and (2). EQU Ic*t1=Id,t2 (3)
Because the constant voltage Vcc is supplied from the constant voltage source 12, the values Ic, Id are expressed by equations (4), (5). EQU Ic=(Vcc-V.sub.F)/R'c (4) EQU Id=(Vcc-V.sub.F)/R'd (5)
Here a value V.sub.F is a diode drop between a base terminal and an emitter terminal in a transistor. As a result, an equation (6) is obtained from the equations (3),(4) and (5). EQU t1/t2=R'c/R'd (6)
Therefore, a charging-discharging time ratio t1/t2 linearly relates to a resistor ratio R'c/R'd.
2.2. Second Previously Proposed Art
FIG. 4 conceptually shows another conventional charging and discharging integration circuit.
As shown in FIG. 4, another conventional charging and discharging circuit 41 is provided with the constant voltage source 12 placed in an IC package 42, first and second resistors 43, 44 arranged in series, an operational amplifier 45 of which an inverting input terminal is connected to a line between the first and second resistors 43,44 and a non-inverting input terminal is connected to a second constant voltage source 46, the capacitor element 15 connected to the inverting input terminal of the operational amplifier 45 and an output terminal of the operational amplifier 45, and a discharging switch 47 for connecting the capacitor element 15 to the constant voltage source 12 through the first resistor 43. A Miller integrating circuit is composed of the operational amplifier 45 placed in the IC package 42 and the capacitor element 15.
The first resistor 43 is connected to an external terminal T6 of the IC package 42, and a divided voltage at the line between the first and second resistors 43,44 is applied to the inverting input terminal of the operational amplifier 45 through an external terminal T7 of the IC package 42. Also, the second constant voltage source 46 is grounded through an external terminal T8 of the IC package 42, and the capacitor element 15 is connected to the output terminal of the operational amplifier 45 through an external terminal T9. Therefore, the five external terminals T3, T6, T7, T8 and T9 are used.
In the above configuration of the conventional charging and discharging integration circuit 41, in cases where the discharging switch 47 is switched off in a charging period, the operational amplifier 45 controls the divided voltage at the line between the first and second resistors 43,44 to a voltage supplied by the second constant voltage source 46. Therefore, the capacitor element 15 is charged by an output current flowing from the constant voltage source 12 through the output terminal of the operational amplifier 45, and the capacitor voltage Vc of the capacitor element is linearly increased. Thereafter, in cases where the discharging switch 47 is switched on in a discharging period, the operational amplifier 45 controls the divided voltage to the voltage supplied by the second constant voltage source 46. Therefore, the capacitor element 15 is discharged through the output terminal of the operational amplifier 45, and the capacitor voltage Vc of the capacitor element is linearly decreased.
2.3. Problems to be Solved by the Invention
However, as shown in FIG. 5, for example, the discharging period corresponds to an angle of 30 degrees for one rotation (360 degrees) of a rotor rotated at a certain rotational speed, and the charging period corresponds to a remaining angle of 330 degrees. Therefore, the charging-discharging time ratio t1/t2 higher than 10 is required, and the constant charging current Ic becomes lower than 1/10 of the constant discharging current Id. Also, the function of the constant charging current circuit 14 as a current mirror circuit is degraded as the constant charging current Ic becomes low. Also, it is required to reduce the capacitance of the capacitor element 15 for the purpose of manufacturing the conventional charging and discharging integration circuit 11 at a low cost, so that absolute values Ic and Id of the constant charging and discharging currents are undesirably reduced.
Accordingly, in cases where the capacitance of the capacitor element 15 is reduced when the charging-discharging time ratio t1/t2 is high, the constant charging current Ic is considerably decreased, and the function of the constant charging current circuit 14 as a current mirror circuit is extraordinarily degraded. Therefore, there is a drawback because the charging and discharging operation in tile conventional charging and discharging integration circuit 11 cannot be performed with high accuracy.
Also, because the capacitor element 15 in the conventional charging and discharging integration circuit 41 is not grounded, a reset circuit for discharging the electric charge of the capacitor element 15 is required in the conventional charging and discharging integration circuit 41, therefore the configuration of the conventional charging and discharging integration circuit 41 is complicated.
In addition, the five external terminals T1 to T5 (or T3, and T6 to T9) are required in the conventional charging and discharging integration circuit 11 (or 41). Therefore, in cases where the conventional charging and discharging integration circuit 11 (or 41), a calculating circuit for the ignition-advance control and a limiter circuit for preventing an excessive rotation of the rotor in the engine are, for example, packed in the IC package 13 (or 42), the number of external terminals easily reaches ten. In this case, a dual inline package is required as the IC package 13 (or 42). In contrast, assuming that the number of external terminals is nine, the conventional charging and discharging integration circuit 11 (or 41), the calculating circuit and the limiter circuit can be packed in a single inline package as the IC package 13 (or 42) to reduce an arranging space of the conventional charging and discharging integration circuit 11 (or 41).
Accordingly, another drawback in the conventional charging and discharging integration circuit 11 (or 41) is that a large arranging space of the conventional charging and discharging integration circuit 11 (or 41) is required because the dual inline package is required.